About the Role

RTL Design Engineer는 AI Chip 또는 SoC 내에서 동작하는 Digital Logic 및 IP를 RTL 수준에서 설계·구현하고, 상위 IP/SoC에 통합될 수 있도록 Front-end Design Flow를 수행하는 포지션입니다.

본 포지션은 Verilog/SystemVerilog 기반 RTL 설계, Verilog RTL Simulation 및 Verification, HDL Simulator를 활용한 Debug, Lint/CDC/Synthesis/ECO 등 Front-end Integration 업무를 담당합니다.

또한 SoC Design, SoC Design Verification, Emulation, STA, Physical Design, Software 및 System 팀과 협업하여 설계된 Digital IP가 시스템 수준에서 안정적으로 동작하고, Silicon 단계까지 높은 품질로 검증될 수 있도록 지원합니다.

Key Responsibilities

Digital Logic 및 IP 설계: AI Chip 또는 SoC 내에서 동작하는 Digital Logic 및 IP를 설계, 구현하고 Debug합니다.

RTL 설계 및 검증 연계: Verilog/SystemVerilog 기반 RTL을 설계하고, HDL Simulator를 활용하여 기능 검증 및 Debug를 수행합니다.

Verilog RTL Simulation 및 Verification: Verilog RTL Simulation을 수행하여 설계 기능을 검증하고, Simulation 결과를 분석하여 RTL 설계 이슈를 식별·개선합니다.

IP Integration: 담당 IP를 상위 IP 또는 SoC 구조에 통합하고, 인터페이스, 제어 로직, 데이터 경로가 시스템 요구사항에 맞게 동작하도록 설계합니다.

Front-end Design Flow 수행: Lint, CDC, Synthesis, ECO 등 Front-end Integration 업무를 수행하고, STA 및 Physical Design 단계와 연계될 수 있도록 설계 품질을 관리합니다.

Design Automation: Python, Perl, Tcl 등 Script 언어를 활용하여 반복적인 설계·검증 업무를 자동화하고 개발 효율을 개선합니다.

Cross-functional Collaboration: SoC Design, SoC Design Verification, Emulation, STA, Physical Design 팀과 협업하여 IP 통합, 검증, Timing Closure 및 Silicon Bring-up 준비를 지원합니다.

Software/System 협업: Software 및 System 팀과 협업하여 HW/SW Interface, Register, Control Flow 등이 시스템 수준에서 안정적으로 동작하도록 지원합니다.

문서화 및 설계 리뷰: 설계 사양서, RTL 설계 문서, Interface 문서, Debug 결과 및 검증 관련 문서를 작성하고 설계 리뷰에 참여합니다.

Qualifications

경력: Digital ASIC/SoC 설계 분야에서 8년 이상의 실무 경험을 보유하신 분

RTL 설계 역량: Verilog/SystemVerilog를 활용한 RTL 설계 및 Debug 경험을 보유하신 분

ASIC/SoC 설계 Flow 이해도: RTL 설계부터 Simulation, Lint, CDC, Synthesis, STA, ECO, Silicon Characterization까지 Digital ASIC/SoC Front-end Design Flow에 대한 이해와 경험을 보유하신 분

사양 분석 역량: Project Specification을 이해하고, 기능 요구사항, Interface 요구사항, 검증 항목을 체계적으로 도출할 수 있는 분

Debug 역량: HDL Simulator를 활용하여 RTL Simulation 결과를 분석하고, 설계 이슈를 Debug한 경험을 보유하신 분

EDA Tool 활용 역량: Synopsys 또는 Cadence 계열 EDA Tool을 활용한 Simulation, Synthesis, Timing(STA), Formal Verification, Assertion-based Verification 관련 경험 또는 이해를 보유하신 분

협업 역량: Design Verification, Emulation, STA, Physical Design, Software, System 팀과 협업하여 설계 품질을 개선한 경험 또는 원활한 커뮤니케이션 역량을 보유하신 분

문서화 역량: 설계 사양서, Interface 문서, Debug Report, Review 자료 등 기술 문서 작성 역량을 보유하신 분

Preferred Qualifications

MCU, DMA, Memory Controller 설계 경험 보유자

Flash, DRAM, SRAM 등 Memory Interface 또는 Memory Controller 설계 경험 보유자

AI Chip, SoC, ASIC 또는 반도체 IP 개발 경험 보유자

ARM 기반 SoC 설계 경험 보유자

ARM 기반 SoC Platform 및 Peripheral IP 설계 경험 보유자 (예: AHB, AXI 기반 SoC Platform 및 Peripheral IP 설계)

AMBA 기반 Bus Interface 설계 경험 보유자 (예: AXI, AHB, APB 등)

Register, Control Logic, FSM, Data Path 설계 경험 보유자

Lint, CDC, Synthesis, STA, ECO 등 Front-end Sign-off Flow 경험 보유자

SystemVerilog Assertion, Formal Verification 또는 Testbench 개발 경험 보유자

Emulation, FPGA Prototyping 또는 Silicon Bring-up 협업 경험 보유자

Python, Perl, Tcl, Shell Script 등을 활용한 설계 자동화 경험 보유자

Software/System 팀과의 HW/SW Interface 협업 경험 보유자

전기전자공학, 반도체공학 또는 관련 전공 석사 또는 박사 학위 보유자

전형절차

서류전형 - 1차 실무 면접 - 2차 컬처핏 면접 - 입사

*영문 입사지원서로 제출하여 주시기 바랍니다. 

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About the Role

The RTL Design Engineer is responsible for designing and implementing Digital Logic and IP that operate within an AI Chip or SoC, and for performing front-end design flow activities to enable integration into higher-level IP or SoC structures.

This position involves RTL design using Verilog/SystemVerilog, Verilog RTL simulation and verification, debugging with HDL simulators, and front-end integration activities such as Lint, CDC, Synthesis, and ECO.

The role also requires collaboration with SoC Design, SoC Design Verification, Emulation, STA, Physical Design, Software, and System teams to ensure that the designed Digital IP operates reliably at the system level and is validated with high quality through the silicon stage.

Key Responsibilities

Digital Logic and IP Design: Design, implement, and debug Digital Logic and IP that operate within an AI Chip or SoC.

RTL Design and Verification Collaboration: Design RTL using Verilog/SystemVerilog and perform functional verification and debugging using HDL simulators.

Verilog RTL Simulation and Verification: Perform Verilog RTL simulation to verify design functionality, analyze simulation results, and identify and resolve RTL design issues.

IP Integration: Integrate assigned IP into higher-level IP or SoC structures, and design interfaces, control logic, and data paths to operate according to system requirements.

Front-end Design Flow Execution: Perform front-end integration activities such as Lint, CDC, Synthesis, and ECO, and manage design quality to ensure smooth handoff to STA and Physical Design stages.

Design Automation: Automate repetitive design and verification tasks using scripting languages such as Python, Perl, and Tcl to improve development efficiency.

Cross-functional Collaboration: Collaborate with SoC Design, SoC Design Verification, Emulation, STA, and Physical Design teams to support IP integration, verification, timing closure, and preparation for silicon bring-up.

Software/System Collaboration: Work with Software and System teams to ensure that HW/SW interfaces, registers, and control flows operate reliably at the system level.

Documentation and Design Review: Prepare design specifications, RTL design documents, interface documents, debug results, and verification-related documentation, and participate in design reviews.

Qualifications

Experience: 8+ years of hands-on experience in Digital ASIC/SoC design.

RTL Design Skills: Experience in RTL design and debugging using Verilog/SystemVerilog.

ASIC/SoC Design Flow Understanding: Understanding of and experience with the Digital ASIC/SoC front-end design flow, from RTL design to Simulation, Lint, CDC, Synthesis, STA, ECO, and Silicon Characterization.

Specification Analysis Skills: Ability to understand project specifications and systematically derive functional requirements, interface requirements, and verification items.

Debugging Skills: Experience analyzing RTL simulation results and debugging design issues using HDL simulators.

EDA Tool Proficiency: Experience with or understanding of Synopsys or Cadence EDA tools for Simulation, Synthesis, Timing (STA), Formal Verification, and Assertion-based Verification.

Collaboration Skills: Experience working with Design Verification, Emulation, STA, Physical Design, Software, and System teams to improve design quality, or strong communication skills for cross-functional collaboration.

Documentation Skills: Ability to prepare technical documents such as design specifications, interface documents, debug reports, and design review materials.

Preferred Qualifications

Experience designing MCU, DMA, or Memory Controller blocks.

Experience designing Memory Interfaces or Memory Controllers for Flash, DRAM, SRAM, or other memory types.

Experience developing AI Chips, SoCs, ASICs, or semiconductor IPs.

Experience in ARM-based SoC design.

Experience designing ARM-based SoC platforms and peripheral IPs, including AHB and AXI-based designs.

Experience designing AMBA-based bus interfaces, such as AXI, AHB, or APB.

Experience designing registers, control logic, FSMs, or data paths.

Experience with front-end sign-off flows such as Lint, CDC, Synthesis, STA, and ECO.

Experience with SystemVerilog Assertion, Formal Verification, or testbench development.

Experience collaborating on Emulation, FPGA Prototyping, or Silicon Bring-up.

Experience with design automation using Python, Perl, Tcl, Shell Script, or other scripting languages.

Experience collaborating with Software/System teams on HW/SW interfaces.

Master’s or Ph.D. degree in Electrical Engineering, Semiconductor Engineering, or a related field.